Parthiban Rajavelu, Kumarasamy Naicker, 2026. "High-Throughput VLSI Architecture for Real-Time LDPC Decoders", International Journal of Electronics and Communication Engineering Research (IJECER) 1(1): 19-37.

As these requirements rise, the need for reliable symbolic and high-speed digital communication systems has seen a large increase leading to advanced error correction mechanisms which provide such support in modern wireless, satellite, optical and data center networks. Low-density parity-check (LDPC) codes are one of the most powerful forward error correction techniques which approach the Shannon limit within a few tenths of decibels, and application oriented LDPC codes; nowadays have become vital for high-data-rate communications. LDPC codes have realized a widespread adoption in multiple communication standards or systems, such as 5G New Radio, Wi-Fi 6, DVB-S2, Optical Communication Systems and Next Generation Broadband Networks. But the computational complexity of LDPC decoding becomes a significant barrier to its real-time implementation for ultra-high throughput, low latency and energy-efficient scenarios. These constraints require design of optimized VLSI architectures for scalable parallelism to accelerate the decoding operations while preserving low error correction capabilities.
A promising technology to tackle these challenges is Reconfigurable Intelligent Surfaces (RIS), which can shape the wireless environment by changing the propagation of electromagnetic waves. RIS technology presents programmable metasurfaces composed of many passive reflective elements that adaptively emulate signal reflections, phase shifts, and beam directions, in contrast to traditional communication systems that regard the propagation environment as uncontrollable. RIS can enhance signal strength, increase coverage area, decrease path loss, and boost spectral efficiency by smartly controlling wireless transmission paths. This enables the communication environment itself to become a dynamic element of the wireless system, and opens up exciting new areas for network performance optimization.
This dissertation explores the high-throughput VLSI architecture design and implementation of real-time LDPC decoders. It analyzes the theory of LDPC encoding and iterative decoding approaches, such as belief propagation, layered decoding and message-passing algorithms. Different architectural strategies have been investigated for accelerating decoder speed, lowering latency, and increasing hardware efficiency. Additionally, we focus on parallel processing approaches, pipelining procedures, memory efficient methods and interconnection network designs which combined give real-time decoding throughput among recent communication systems.
The presented research investigates FPGA- and ASIC-based LDPC implementation paths for high-throughput decoders, with a performance comparison based on throughput, hardware utilization, power efficiency and decoding accuracy. In this regard, high-level scheduling and resources allocation approaches are explored to optimize the computation while keeping the implementation simpler. In addition, recent advances in emerging technologies for error correction, like artificial intelligence-assisted decoding and machine learning-based optimization are also studied as potential improvement methods for the new LDPC decoder architectures to be developed.

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